=== serv ===
HEAD: 2026-08-25 14:38 | LICENSE: LICENSE | README: Y
RTL files: 78 | RTL lines: 6701 | TB rtl files: 0 | doc files: 14
FuseSoC .core: 4 | Makefile: 2 | .py: 4 | .tcl: 10 | bazel-ish: 0 | cmake: 5
CI workflows: 5 ['openlane.yml', 'lint.yml', 'ci.yml', 'pages.yml']
submodules(0): []
top dirs: ['.github', 'bench', 'data', 'doc', 'rtl', 'servant', 'servile', 'serving', 'sw', 'verif', 'zephyr']

=== neorv32 ===
HEAD: 2026-09-06 08:37 | LICENSE: LICENSE | README: Y
RTL files: 74 | RTL lines: 28094 | TB rtl files: 0 | doc files: 25
FuseSoC .core: 0 | Makefile: 38 | .py: 0 | .tcl: 1 | bazel-ish: 0 | cmake: 0
CI workflows: 3 ['Processor.yml', 'Verilog.yml', 'Documentation.yml']
submodules(0): []
top dirs: ['.github', 'docs', 'rtl', 'sim', 'sw']

=== picorv32 ===
HEAD: 2026-07-31 17:45 | LICENSE: tests/LICENSE | README: Y
RTL files: 41 | RTL lines: 9133 | TB rtl files: 0 | doc files: 4
FuseSoC .core: 5 | Makefile: 11 | .py: 8 | .tcl: 8 | bazel-ish: 0 | cmake: 0
CI workflows: 1 ['ci.yml']
submodules(0): []
top dirs: ['.github', 'dhrystone', 'firmware', 'picosoc', 'scripts', 'tests']

=== ibex ===
HEAD: 2026-08-31 07:52 | LICENSE: LICENSE | README: Y
RTL files: 654 | RTL lines: 109042 | TB rtl files: 266 | doc files: 120
FuseSoC .core: 209 | Makefile: 50 | .py: 200 | .tcl: 24 | bazel-ish: 7 | cmake: 0
CI workflows: 5 ['private-ci.yml', 'cla.yml', 'ci.yml', 'ci-formal.yml']
submodules(0): []
top dirs: ['.github', 'ci', 'doc', 'dv', 'examples', 'formal', 'lint', 'nix', 'rtl', 'shared', 'syn', 'util', 'vendor']

=== VexRiscv ===
HEAD: 2026-08-31 17:50 | LICENSE: LICENSE | README: Y
RTL files: 122 | RTL lines: 27279 | TB rtl files: 13 | doc files: 8
FuseSoC .core: 0 | Makefile: 34 | .py: 5 | .tcl: 9 | bazel-ish: 0 | cmake: 0
CI workflows: 1 ['scala.yml']
submodules(1): ['src/test/resources/VexRiscvRegressionData']
top dirs: ['.github', 'assets', 'doc', 'project', 'scripts', 'src']

=== e203_hbirdv2 ===
HEAD: 2025-08-06 10:51 | LICENSE: LICENSE | README: Y
RTL files: 141 | RTL lines: 57651 | TB rtl files: 1 | doc files: 20
FuseSoC .core: 2 | Makefile: 13 | .py: 12 | .tcl: 16 | bazel-ish: 0 | cmake: 0
CI workflows: 1 ['deploy_doc.yaml']
submodules(0): []
top dirs: ['.github', 'doc', 'fpga', 'pics', 'riscv-tools', 'rtl', 'tb', 'vsim']

=== pulpino ===
HEAD: 2019-05-29 11:29 | LICENSE: LICENSE | README: Y
RTL files: 49 | RTL lines: 10608 | TB rtl files: 12 | doc files: 23
FuseSoC .core: 0 | Makefile: 51 | .py: 22 | .tcl: 25 | bazel-ish: 0 | cmake: 118
CI workflows: 0 []
submodules(0): []
top dirs: ['ci', 'doc', 'fpga', 'ips', 'rtl', 'sw', 'tb', 'vsim']

=== pulpissimo ===
HEAD: 2024-05-30 19:02 | LICENSE: LICENSE.md | README: Y
RTL files: 107 | RTL lines: 87497 | TB rtl files: 11 | doc files: 52
FuseSoC .core: 1 | Makefile: 46 | .py: 42 | .tcl: 70 | bazel-ish: 0 | cmake: 0
CI workflows: 1 ['gitlab-ci.yml']
submodules(2): ['sw/pulp-runtime', 'sw/regression_tests']
top dirs: ['.github', 'doc', 'hw', 'sw', 'target', 'utils']

=== opentitan ===
HEAD: 2026-09-04 20:21 | LICENSE: LICENSE | README: Y
RTL files: 3995 | RTL lines: 1156179 | TB rtl files: 2670 | doc files: 885
FuseSoC .core: 821 | Makefile: 31 | .py: 667 | .tcl: 137 | bazel-ish: 794 | cmake: 0
CI workflows: 12 ['cherrypick.yml', 'private-ci.yml', 'pr_change_check.yml', 'monthly.yml']
submodules(0): []
top dirs: ['.github', 'ci', 'doc', 'hw', 'quality', 'release', 'rules', 'signing', 'site', 'sw', 'third_party', 'toolchain', 'util']